Patent Document 1 discloses a control circuit for a switching power supply apparatus including an on-blanking pulse generating circuit. The on-blanking pulse generating circuit outputs a blanking pulse signal that ensures that a switching element is not turned off for a fixed interval of time after the switching element has been turned on.
One form of a conventional switching power supply apparatus having a blanking function will be described with reference to FIG. 6. FIG. 6 shows a switching power supply apparatus 1 configured as a flyback DC-DC converter. In the switching power supply apparatus 1, the output voltage is controlled by PWM (pulse width modulation), and the output is stabilized by a current mode control method. An alternating current power supply AC and a load L is connected to the switching power supply apparatus 1.
In the switching power supply apparatus 1, an alternating current supplied from the alternating current power supply AC is full-wave rectified by a bridge diode BD1. The direct current converted by such full-wave rectification is smoothed by a capacitor C1, and then supplied to the series circuit of a primary-side winding Tn1 of an output transformer T1 and a switching element PT1. The switching element PT1 is, for example, an N-type power MOSFET. A control circuit 2 controls the switching operation of the switching element PT1 such that a pulsating current is generated in the secondary-side winding Tn2 of the output transformer T1. This pulsating current is rectified by a diode D2 and smoothed by a capacitor C3, thereby converted into a direct current. This direct current is supplied to the load L.
The switching power supply apparatus 1 includes a voltage detection circuit VDC for detecting an output voltage to the load L. To this voltage detection circuit VDC, a light-emitting element PC1a of a photo coupler is connected in parallel. A light-receiving element PC1b of the photo coupler is connected to a feedback terminal FB provided in the control circuit 2. The detection value of the voltage detection circuit VDC is input as a feedback signal to the feedback terminal FB of the control circuit 2 via the photo coupler.
The control circuit 2 also includes a power supply terminal VCC to which a power supply voltage is input. Specifically, the voltage input to the power supply terminal VCC is a direct current voltage obtained by converting the output of an auxiliary winding Tn3 of the output transformer T1 through rectification by a diode D1 and smoothing by a capacitor C2.
The control circuit 2 also includes a current detection terminal CS to which a current detection signal is input. The current detection signal indicates a voltage into which the current flowing through the switching element PT1 is converted by a current detection resistor Rs.
The control circuit 2 also includes an output terminal OUT for outputting a switching control signal for controlling the switching operation of the switching element PT1. This switching control signal is applied to the gate of the switching element PT1. The control circuit 2 further includes a ground terminal GND connected to ground level.
FIG. 7 shows the configuration of the control circuit 2. An oscillator circuit 3, provided in the control circuit 2, outputs a clock signal Clock. The clock signal Clock is input to a blanking pulse generating circuit 4. The blanking pulse generating circuit 4 outputs a blanking pulse signal T_blank. The blanking pulse signal T_blank is input to a set terminal of a set-dominant RS flip-flop circuit RS-FF1. The blanking pulse generating circuit 4 and the blanking pulse signal T_blank will be described more later.
The RS flip-flop circuit RS-FF1 outputs a switching control signal. The switching control signal is sent to the output terminal OUT of the control circuit 2 by way of a buffer B. The output terminal OUT of the control circuit 2 is connected to the gate of the switching element PT1 by way of a limiting resistor RO. With this configuration, when the voltage of the switching control signal is high level, the switching element PT1 is turned on.
The control circuit 2 further includes a current detection comparator COMP and a slope generation circuit 5. The current detection signal is input to the positive input terminal (non-inverting input terminal) of the current detection comparator COMP by way of the current detection terminal CS. The slope signal V_slope output from the slope generation circuit 5 is input to the negative input terminal (inverting input terminal) of the current detection comparator COMP. The current detection comparator COMP compares the current detection signal with the slope signal V_slope and outputs a comparison signal corresponding to a result of the comparison. The comparison signal is input to a reset terminal of the RS flip-flop circuit RS-FF1.
When the current detection signal exceeds the slope signal V_slope, the current detection comparator COMP outputs a high-level comparison signal. Upon receiving this high-level comparison signal, the RS flip-flop circuit RS-FF1 is reset. As a result, the output of the RS flip-flop circuit RS-FF1 becomes low level, and the switching element PT1 becomes turned off in response.
The control circuit 2 also includes a feedback circuit 6 connected to the power supply terminal VCC, the feedback terminal FB, the ground terminal GND, the oscillator circuit 3, and the slope generation circuit 5. The feedback circuit 6 includes a bipolar transistor BT61, diodes D61 and D62, and resistors R61 to R65. The bipolar transistor BT61 constitutes an emitter follower circuit for the internal power supply (5 V), and supplies a voltage (5 V, which is the forward voltage of the diode having a base and an emitter) based on the internal power supply (5 V) to a circuit formed of the diodes D61, D62 and the resistors R61 to R65. The resistor R61 pulls up the light receiving element PC1b of the photo coupler. The voltage (feedback signal) of the feedback terminal FB is obtained by dividing the output voltage (5 V, which is the forward diode voltage) of the emitter follower circuit formed of the bipolar transistor BT61 between the resistor R61 and the on resistance of the light receiving element PC1b of the photo coupler. Here, as the output voltage increases, the amount of light emitted from the light-emitting element PC1a of the photo coupler increases, and the on resistance of the light receiving element PC1b falls. As a result, the voltage (feedback signal) of the feedback terminal FB decreases. On the other hand, as the output voltage decreases, the amount of light emitted by the light emitting element PC1a of the photo coupler decreases, and the on resistance of the light receiving element PC1b rises. As a result, the voltage (feedback signal) of the feedback terminal FB increases.
The feedback circuit 6 outputs the voltage (feedback signal) VFB of the feedback terminal FB to the oscillator circuit 3 via the diode D61. In addition, the feedback circuit 6 outputs, to the slope generation circuit 5, a signal obtained by reducing the voltage (feedback signal) VFB of the feedback terminal FB using the diode D62 and then dividing the resultant voltage using a voltage dividing circuit including the resistors R62 to R65 (signal thus obtained will be simply referred to as a voltage-divided signal or voltage-divided value, below).
As the load L decreases, the output voltage to the load L will increase accordingly. As a result, the feedback signal VFB, which is the voltage of the feedback terminal FB, decreases as described above.
The slope generation circuit 5 outputs the slope signal V_slope, which corresponds to a signal input from the voltage-dividing circuit in the feedback circuit 6. While not described in detail, the slope generation circuit 5 is configured to output, as the slope signal V_slope, a signal obtained by adding a signal for monotonic decrease to the voltage-divided value of the feedback signal VFB (thus, the signal output by the slope generation circuit 5 monotonically decreases from its initial value, i.e., the voltage-divided value of the feedback signal VFB) in order to prevent subharmonic oscillation (switching frequency fluctuation in the audible frequency range). This slope signal is compared with the current detection signal in the current detection comparator COMP. In accordance with the comparison, the duty cycle of the switching control signal output from the output terminal OUT is set such that the switching power supply apparatus 1 outputs a voltage of a set value without generating any audible noises.
Next, referring to FIG. 8, the configuration of the current detection comparator COMP will be described. The current detection comparator COMP operates with a voltage supply of 5 V. The voltage of 5 V is supplied to constant current sources bias1 and bias2 in the current detection comparator COMP.
The positive input terminal and the negative input terminal of the current detection comparator COMP are connected to the gate of a P-type MOS transistor P2 and the gate of a P-type MOS transistor P1, respectively. The constant current source bias1 is connected to the sources of the P type MOS transistors P1 and P2. The P-type MOS transistors P1 and P2 form a differential pair.
A current mirror circuit MC including N-type MOS transistors N1 and N2 is connected to the drains of the P-type MOS transistors P1 and P2. The sources of the transistors N1 and N2 are both connected to ground. The drain and the gate of the transistor N1 are connected to each other and serve as the input terminal of the current mirror circuit MC. The drain of the transistor N2 corresponds to the output terminal of the current mirror circuit MC.
An N-type MOS transistor N3 is connected to ground and to the constant current source bias2. The gate of the N-type MOS transistor N3 is connected to the drains of the P-type MOS transistor P2 and the N-type MOS transistor N2. The drain of the N-type MOS transistor N3 and the constant current source bias2 are connected to the output terminal comp out of the current detection comparator COMP.
The constant current source bias1, the P-type MOS transistors P1 and P2 of the differential pair, and the N-type MOS transistors N1 and N2 constitute a differential portion of the current detection comparator COMP. The constant current source bias2 and the N-type MOS transistor N3 constitute an output portion of the current detection comparator COMP. One output of the differential portion (the drain of the P-type MOS transistor P2) is input to the output portion.
Here, referring back to FIG. 6, when the switching element PT1 is turned on, a surge current is generated by discharge of the capacitance of the main circuit, a gate drive current, or the like. This surge current brings the voltage of the comparison signal of the current detection comparator COMP to high level. If the RS flip-flop circuit RS-FF1 is reset in response, the terminal voltage of the output terminal OUT becomes low level. As a result, the switching element PT1 is turned off. In other words, in such case, the switching element PT1 is turned off immediately after being turned on, which means that the switching power supply apparatus 1 is not normally controlled.
To avoid such a situation, the blanking pulse generating circuit 4 shown in FIG. 7 is provided. The blanking pulse generating circuit 4 generates the blanking pulse signal T_blank whose voltage is kept at high level for a predetermined period from the rise of the clock signal Clock of the oscillator circuit 3. Such predetermined period may be referred to as a blanking period. The blanking period is around several hundred nanoseconds, for example.
As described above, the blanking pulse signal T_blank is input to the set terminal of the set-dominant RS flip-flop circuit RS-FF1. Thus, in the blanking period, the terminal voltage of the output terminal OUT is kept at high level independently of the comparison signal from the current detection comparator COMP.
FIG. 9 shows the configuration of the blanking pulse generating circuit 4. The input terminal 41 of the blanking pulse generating circuit 4 is connected to the set terminal of a reset-dominant RS flip-flop circuit RS-FF2 and the input terminal of an inverter INV1. The output terminal of the inverter INV1 is connected to the input terminal of the inverter INV2 and the output terminal of the inverter INV2 is connected to the reset terminal of the RS flip-flop circuit RS-FF2 via a resistor R11. The Q output terminal of the RS flip-flop circuit RS-FF2 is connected to the output terminal 42 of the blanking pulse generating circuit 4.
The blanking pulse generating circuit 4 further includes an N-type MOS transistor N91. The drain of the N-type MOS transistor N91 is connected to the output side of the resistor R11 and to the reset terminal of the RS flip-flop circuit RS-FF2. The source of the N-type MOS transistor N91 is connected to ground. The gate of the N-type MOS transistor N91 is connected to the output terminal of the inverter INV1.
The blanking pulse generating circuit 4 further includes a capacitor C11. One end of the capacitor C11 is connected to the drain of the N-type MOS transistor N91 and to the reset terminal of the RS flip-flop circuit RS-FF2. The other end of the capacitor C11 is connected to ground.
FIG. 10 is a timing chart showing the operation of the blanking pulse generating circuit 4. In FIG. 10, (a) shows changes in the clock signal Clock (having a period dt), and (b) shows changes in an output INV1_out of the inverter INV1. Also, (c) shows changes in a reset signal Reset input to the reset terminal of the RS flip-flop circuit RS-FF2, and (d) shows changes in the blanking pulse signal T_blank. The reference symbol BL indicates a blanking period.
When the clock signal Clock is low level, the output INV1_out of the inverter INV1 is high level. Accordingly, the N-type MOS transistor N91 is turned on (conductive), so that the reset signal Reset of the RS flip-flop circuit RS-FF2 is low level. Meanwhile, the set of the RS flip-flop circuit RS-FF2 is also low level. Thus, the RS flip-flop circuit RS-FF2 holds the current state.
When the clock signal Clock rises to high level under these conditions, the set signal of the RS flip-flop circuit RS-FF2 becomes high level, so that the RS flip-flop circuit RS-FF2 is set. In response, the blanking pulse signal T_blank, which is the Q output of the flip-flop circuit RS-FF2, becomes high level.
Meanwhile, when the clock signal Clock becomes high level, the output INV1_out of the inverter INV1 becomes low level and the output INV2_out of the inverter INV2 becomes high level, so that the N-type MOS transistor N91 is turned off (cutoff). Thus, the high-level output INV2_out of the inverter INV2 is applied to a time constant circuit comprising the resistor R11 and the capacitor C11. As a result, the reset signal Reset of the RS flip-flop circuit RS-FF2, which is the charge voltage of the capacitor C11, is rising.
When the reset signal Reset rises and reaches the threshold voltage (2.5 V shown in (c) of FIG. 10) for the reset terminal of the RS flip-flop circuit RS-FF2, the RS flip-flop circuit RS-FF2 recognizes that its reset input becomes high. At that time, the set input of the RS flip-flop circuit RS-FF2 is high level, too. However, being reset-dominant, the RS flip-flop circuit RS-FF2 is reset. In response, the blanking pulse signal T_blank, which is the Q output of the flip-flop circuit RS-FF2, becomes low level.
Then, when the clock signal Clock falls to low level, the reset input and the set input of the RS flip-flop circuit RS-FF2 simultaneously become low level as described above. Thus, the blanking pulse signal T_blank, which is the Q output of the flip-flop circuit RS-FF2, maintains low level.
Next, the operation of the control circuit 2 under heavy load will be described with reference to FIG. 11. In FIG. 11, (a) shows the clock signal Clock (having the period dt) of the oscillator circuit 3, and (b) shows the blanking pulse signal T_blank. Also, (c) shows the slope signal V_slope and the voltage VCS (i.e., the terminal voltage of the current detection terminal CS) corresponding to the current flowing through the switching element PT1. In FIG. 11, “VFB” represents the voltage of the feedback terminal FB and “Vf” represents the forward voltage of the diode provided in the voltage-dividing circuit of the feedback circuit 6. Also, “/4” in “(VFB−Vf)/4” indicates that the voltage division ratio between the resistors R62 to R65 is 1/4. In addition, (d) shows the comparison signal outputted by the current detection comparator COMP, and (e) shows the voltage VOUT of the output terminal OUT of the control circuit 2. Note that, in FIG. 11, the voltage of the power supply terminal VCC, i.e., the power supply voltage, is also represented by VCC.
First, at time point t0, the clock signal Clock rises. In response, the blanking pulse signal T_blank becomes and remains high level during a period from time point t0 to time point tB. The period from time point t0 to time point tB is the blanking period BL. When the blanking pulse signal T_blank becomes high level, the RS flip-flop circuit RS-FF1 is set and the voltage VOUT becomes high level. In response, the switching element PT1 becomes turned on, and a surge voltage SG due to a surge current is generated. As a result, the output of the current detection comparator COMP becomes and remains high level from time point t0 to time point t1, and goes back to low level after that. Here, time point t1 is prior to time point tB. As described above, the blanking period is set longer than the surge current generation period so that the influence of the surge voltage SG due to the surge current ends during the blanking period. During the blanking period, the high-level blanking pulse signal T_blank is input as a set signal to the RS flip-flop circuit RS-FF1. Being set-dominant, the RS flip-flop circuit RS-FF1 maintains its output at high level during the blanking period. Thus, the voltage VOUT also maintains high level independently of the comparison signal of the current detection comparator COMP.
Then, at time point t2, which is later than time point tB, the voltage VCS exceeds the slope signal V_slope. The detection that the voltage VCS has exceeded the slope signal V_slope after the end of the blanking period is also referred to as normal current detection. Upon the normal current detection, the comparison signal of the current detection comparator COMP becomes high level, and the voltage VOUT becomes low level. Thus, the voltage VOUT is kept at high level from time point t0 to time t2. When voltage VOUT becomes low level, the switching element PT1 becomes turned off. In response, the voltage VCS, which is the current detection signal, goes back to low level.
The duty cycle (on-time ratio) of the voltage VOUT can be expressed as (t2−t0)/dt. Under heavy load, the duty cycle of the voltage VOUT is relatively large. Thus, the period from time point tB at which the blanking period BL ends to time point t2 at which the voltage VOUT becomes the low level is relatively long.
Next, the operation of the control circuit 2 under light load will be described with reference to FIG. 12. As shown in FIG. 12, a surge voltage SG due to a surge current is generated during the blanking period BL (period from time point t0 to time point tB). Such generation of the surge voltage SG due to the surge current brings the comparison signal of the current detection comparator COMP to high level.
After the surge current generation, the comparison signal is going back to low level. However, before actually reaching the threshold voltage of the reset terminal of the RS flip-flop circuit RS-FF1 (the comparison signal is determined to be low level if it is lower than that threshold voltage), the comparison signal rises again. This is because the comparator COMP, which has a limited slew rate, superimposes an impact of a rapid increase of the voltage VCS on the comparison signal at that time. Therefore, the comparison signal is kept at high level during the period (period from time point t0 to time point t3) until the voltage VCS exceeds the slope signal V_slope at time point t3 immediately after the end of the blanking period, that is, at time point t3 of normal current detection. On the other hand, the blanking period BL ends at time point tB, which is prior to time point t3. Thus, at time point tB, the comparison signal resets the RS flip-flop circuit RS-FF1, and the voltage VOUT becomes low level.
In FIG. 12, (c) shows the comparison signal SIG of the current detection comparator COMP and the input threshold TH of the reset terminal of the RS flip-flop circuit RS-FF1. Note that the levels of the comparison signal SIG and the input threshold TH are shown smaller than the actual values so as to be comparable to that of the slope signal V_slope. In response to the surge current detection, the voltage of the comparison signal SIG exceeds the input threshold TH and becomes high level. After that, the voltage of the comparison signal SIG decreases, but rises again due to normal current detection before falling below the input threshold TH. In other words, the voltage of the comparison signal SIG does not fall below the input threshold TH in the period from the surge current detection to the normal current detection. In FIG. 10, (d) shows the low/high of the comparison signal SIG recognized by the reset terminal of the RS flip-flop circuit RS-FF1 to which the comparison signal SIG is input.
In the control circuit 2 shown in FIG. 7, the comparison signal is originally intended to become high level by detection of the surge voltage SG due to the surge current, then go back to low level once, and becomes high level again in response to the normal current detection, regardless of the length of the period from the surge current detection to the normal current detection. Accordingly, the voltage VOUT is originally intended to be kept at high level from time point t0 to time point t3, which is the normal current detection timing.
However, in practice, as shown in FIG. 12, when the period from the surge current detection to the normal current detection is short, the comparison signal becomes high level in response to detection of the surge voltage SG due to the surge current and remains high level until the next normal current detection, since the slew rate of the comparator COMP is not infinite. As a result, the voltage VOUT maintains high level not during the period from time point t0 to time point t3, but only in the period from time point t0 to time point tB, which is prior to time point t3.
As described above, the period during which the voltage VOUT is kept at high level, i.e., the ON time of the switching element PT1, is equal to the blanking period BL, which is shorter than the intended ON time. This is because the current detection comparator COMP cannot distinguish between surge current detection and normal current detection if an interval from surge current detection to normal current detection is too short.
FIG. 13 shows the relationship between the magnitude of the load and the ON time of the switching element PT1. In FIG. 13, it is assumed that load magnitudes LO1 and LO2 are both light, and the load magnitude LO1 is lighter than the load magnitude LO2. Also, it is assumed that time period TO1 is shorter than time period TO2. Further, the relationship between the magnitude of the load and the intended ON time is indicated by dotted line G1, and the relationship between the magnitude of the load and the actual ON time is indicated by solid line G2.
As indicated by dotted line G1, the intended ON time when the magnitude of the load is equal to or less than LO1 is time TO1. Time TO1 has a length equal to the blanking period BL. When the magnitude of the load is larger than LO1, the intended ON time increases linearly as the magnitude of the load increases. The intended ON time when the magnitude of the load is equal to LO2 is time TO2.
As indicated by solid line G2, the actual ON time when the magnitude of the load is equal to or less than LO1 is time TO1, which is equal to the intended ON time. When the magnitude of the load is larger than LO1 and smaller than LO2, the actual ON time is time TO1, which is shorter than the intended ON time. When the magnitude of the load is LO2, the actual ON time irregularly goes up and down between time TO1 and time TO2. When the magnitude of the load is larger than LO2, the actual ON time increases linearly as the magnitude of the load increases, like the intended ON time.
As described above, when the magnitude of the load is larger than LO1 and smaller than LO2, the actual ON time is shorter than the intended ON time. Moreover, when the magnitude of the load is around LO2, the actual ON time irregularly goes up and down between time TO1 and time TO2. In other words, the actual duty cycle does not change continuously. Such irregular and discontinuous change of the duty cycle might cause sound (audible sound) generation in the switching power supply apparatus 1 (when the discontinuous change between time TO1 and time TO2 is subjected to Fourier transform, the resultant frequencies may include ones in the audible range).